The present invention belongs to a technique related with a program modification feature in a microprocessor.
A microprocessor receives instructions composing a program from a storage device, and decodes the instructions with the decoder to control its constituent device such as a calculation device, an input device, an output device, a storage device, or a control device depending on the contents of the instructions, thereby to proceed processes in sequence. The microprocessor which is referred to in this specification includes a microcomputer, a micro controller and a digital signal processor.
FIG. 11 is a diagram showing the rough structure of a general microprocessor. As shown in the diagram, the program counter 10 supplies an instruction storage unit 100 composed of a ready-only-member (ROM) 101, or random-access-memory (RAM), with the address of an instruction to be executed next. The instruction storage unit 100 outputs instruction data in accordance with the received address to a decoder 40. Through these operations, the processes are executed in sequence.
Assume that the program stored in the ROM 101 composing the instruction storage unit 100 contains a bug or a modification of specification. In this case, it is impossible to modify the contents of the program stored in the ROM 101 after the fabrication of the microprocessor, so that the program modification requires the make-over of the microprocessor with a new ROM. This undesirably boosts the cost of manufacturing and delays the delivery of the product.
In order to eliminate the need for the make-over, conventional microprocessors have a program modification feature that enables the program to be modified even after the fabrication of the microprocessors.
FIG. 12 shows the structure of a microprocessor with a conventional program modification feature. In the structure, the program counter 10 supplies the instruction storage unit 100 with an instruction address via an instruction address bus. The instruction storage unit 100 includes the ROM 101 which has programs stored. In the instruction modification unit 110, a modifying address storage unit 111 holds the address value to be modified, and a substitutive instruction storage unit 112 holds the substitutive instruction data to be substituted for an instruction with a bug. An address comparator 113 compares the address value held in the modifying address storage unit 111 with the address value outputted from the program counter 10 every machine cycle and supplies an instruction selector 114 with an address match signal indicating whether or not these values match with each other. The instruction selector 114 selects the substitutive instruction data stored in the substitutive instruction storage unit 112 when the address match signal indicates the match between the address values, and selects the instruction data stored in the instruction storage unit 100 when the signal indicates the mismatch between the address values so as to output the instruction data to the decoder 40.
As described hereinbefore, the conventional program modification feature is achieved as follows: a modifying address which is the address of an instruction to be modified and a substitutive instruction are held in a pair, and when the instruction address outputted from the program counter 10 matches with the modifying address, the instruction data of the instruction address is substituted by the substitutive instruction data and supplied to the decoder 40.